Regviz

Silicon Labs /EFR32FG23B010F128GM40 /RAC_NS /IFADCPLLEN

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as IFADCPLLEN

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Silicon Labs/EFR32FG23B010F512IM40/RAC_NS/IFADCPLLEN#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (disable)IFADCPLLENBBDET 0 (disable)IFADCPLLENBBXLDET 0 (disable)IFADCPLLENBBXMDET 0 (disable)IFADCPLLENCFDET 0 (disable)IFADCPLLENROTDET 0 (disable)IFADCPLLSERIEREGENABLE 0 (disable)IFADCPLLSHUNTREGENABLE 0 (disable)IFADCPLLENREFBUF 0 (disable)IFADCPLLENXOBYP

IFADCPLLENBBDET=disable, IFADCPLLENCFDET=disable, IFADCPLLENXOBYP=disable, IFADCPLLENROTDET=disable, IFADCPLLSHUNTREGENABLE=disable, IFADCPLLENBBXMDET=disable, IFADCPLLENREFBUF=disable, IFADCPLLSERIEREGENABLE=disable, IFADCPLLENBBXLDET=disable

Description

No Description

Fields

IFADCPLLENBBDET

IFADCPLLENBBDET

0 (disable): undefined

1 (enable): undefined
IFADCPLLENBBXLDET

IFADCPLLENBBXLDET

0 (disable): undefined

1 (enable): undefined
IFADCPLLENBBXMDET

IFADCPLLENBBXMDET

0 (disable): undefined

1 (enable): undefined
IFADCPLLENCFDET

IFADCPLLENCFDET

0 (disable): undefined

1 (enable): undefined
IFADCPLLENROTDET

IFADCPLLENROTDET

0 (disable): undefined

1 (enable): undefined
IFADCPLLSERIEREGENABLE

IFADCPLLSERIEREGENABLE

0 (disable): undefined

1 (enable): undefined
IFADCPLLSHUNTREGENABLE

IFADCPLLSHUNTREGENABLE

0 (disable): undefined

1 (enable): undefined
IFADCPLLENREFBUF

IFADCPLLENREFBUF

0 (disable): undefined

1 (enable): undefined
IFADCPLLENXOBYP

IFADCPLLENXOBYP

0 (disable): undefined

1 (enable): undefined

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data